Measurement of the Higgs mass via the channel : e+e- -> ZH -> e+e- + X

In this communication, the mass declined for the decay channel, e+e- -> ZH -> e+e- + X, as measured by the ILD detector was studied. The Higgs mass is assumed to be 120 GeV and the center of mass energy is 250 GeV. For an integrated luminosity of 250 fb-1, the accuracy of the reconstruction and the good knowledge of the initial state allow for the measurement of the Higgs boson mass with a precision of about 100 MeV.Comment: 7 pages, 14 figures, LCWS/ILC 2010 (International Linear Collider Workshop 2010 LCWS10 and ILC10

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout

The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000)

Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design

A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications

International audienc

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

International audienceA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A low power and low signal 5-bit 25MS/s pipelined ADC for monolithic active pixel sensors

For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, made of eight ADC channels. The maximum sampling rate is 25MS/s. The total DC power consumption is 1.7mW/channel on a 3.3V supply voltage recommended for the process. But at a reduced 2.5V supply, it consumes only 1.3mW. The size of each ADC channel layout is only 43μm*1.43mm. This corresponds to the pitch of two pixel columns each one would be 20μm wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1μs; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle

Electronic tests of the barrel presampler mother boards

The electrical characteristics of the barrel presampler mother boards are recalled. The results of the tests of the first full-size mother board are presented. They satisfy our specifications

Electrical tests of e. m. barrel presampler sectors

A description of the tests and electronics used to control the presampler sectors, before and after their assembly, is given. An example of the results obtained for the first two sectors, tested at room and liquid nitrogen temperatures, is shown